FPGA Optimization

C-level Optimization such as in Impulse C

1. Limit the amount of hardware resources used by introducing loops.
2. Split arrays for multiple storage accesses. Storage for each array can be constructed to stream directly into local computation unit, i.e. parallel local memory accesses. Note that register bank can be read by many sources in the same cycle. Thus, small & hot data should go into register.
3. Improve communication performance by fully utilizing the CPU-FPGA bus width. Transfer more bits at a time matching the CPU-FPGA bus width. DMA is another feasible mechanism for communication. But it will hog the bus if you do it too frequently.
4. Loop unrolling to realize higher parallelism using more gates in FPGA.
5. Pipelining in main loop to close the communication gaps of different iterations due to data loading & flushing.

Reference: Optimizing Impulse C Code for Performance by Scott Thibault & David Pellerin.

Logic-level Optimization in Boolean Network model

• Restructuring operations.
  • Reduce dependent inputs.
  • Factorize.
  • Substitute.
  • Eliminate.
• Node minimization.
  • Minimize using dont-care inputs.
  • ...